Chip-size package technology for semiconductors

Microwave Journal

Volumn 41, Issue 5, 1998, Pages 280-294

  Light, David ^a   Faraci, Anthony ^a   Fjelstad, Joe ^a  

^a Tessera Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; PRODUCT DESIGN;

BALL GRID ARRAYS (BGA); CHIP SCALE PACKAGING (CSP);

ELECTRONICS PACKAGING;

EID: 0032074335     PISSN: 01926225     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. Glenda Derman, "Interconnects and Packaging, Part One: Chip-Scale Packages," Electronic Engineering Times, Monday, February 26, 1996.
2. Glenda Derman, "Chip-size Packages Proliferate," Electronic Engineering Times, December 15, 1996.
3. Tom DiStefano and Edwin Heacox, "Designing a Modular Chip-scale Package Assembly Line," Circuits Assembly, March 1997.
4. Tom DiStefano, "Design, Material, Process, Reliability and Manufacturing Transfer of BGA," NEPCON West, February 24, 1997.
5. J. Fjelstad and J.P. Clech, "Reliability Prediction Modeling of Area Array CSPs," Electronic Packaging and Production, June 1997.
6. A.D. Fraser, O.C. Bell and C.T. Strouth, "Electrical Characterization fo Ball Grid Array (BGA) Packages," 1996 High Perfosmance System Design Conference.