Experimental characterization of bit error rate and pulse jitter in RSFQ circuits

IEEE Transactions on Applied Superconductivity

Volumn 11, Issue 1 I, 2001, Pages 529-532

  Bunyk, P ^a   Zinoviev, D ^a  

^a STONY BROOK UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BIT ERROR RATE; COMPUTER SIMULATION; DIGITAL COMPUTERS; ELECTRIC INVERTERS; INTERFEROMETRY; LOGIC CIRCUITS; SCHEMATIC DIAGRAMS; SUPERCONDUCTING ELECTRIC LINES; TIMING JITTER;

ARITHMETIC LOGIC UNIT; CARRY LOOK AHEAD ADDER; JOSEPHSON TRANSMISSION LINES; PULSE JITTER; RAPID SINGLE FLUX QUANTUM CIRCUITS;

JOSEPHSON JUNCTION DEVICES;

EID: 0035269075     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.919399     Document Type: Conference Paper

References (7)

1. Next generation Nb superconductor integrated circuit process
2. FLUX chip: Design of a 20-GHz 16-bit ultrapipelined processor prototype based on 1.75-um LTS RSFQ technology
3. Case study in RSFQ design: Fast pipelined 32-bit adder
4. HYPRES design rules
5. Pulse jitter and timing errors in RSFQ circuits
6. RSFQ logic/memory family: A new Josephson junction technology for sub-teraherz clock frequency digital systems
7. Error rate of a superconducting circuit