Tools for the computer-aided design of multigigahertz superconducting digital circuits

IEEE Transactions on Applied Superconductivity

Volumn 9, Issue 1, 1999, Pages 18-38

  Gaj, Kris ^b   Herr, Quentin P ^c   Adler, Victor ^d   Krasniewski, Andy ^a,e   Friedman, Eby G ^f   Feldman, Marc J ^f  

^a IEEE

^b Krasnow Institute for Advanced Study   (United States)

^c NORTHROP GRUMMAN CORPORATION   (United States)

^d SUN MICROSYSTEMS   (United States)

^e WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^f University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

INDUCTANCE EXTRACTION; SUPERCONDUCTING DIGITAL CIRCUITS;

SUPERCONDUCTING DEVICES;

EID: 0032653090     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.763251     Document Type: Article

References (83)

1. K. K. Likharev, "Ultrafast superconductor digital electronics: RSFQ technology roadmap," Czechoslovak J. Phys., Suppl. S6, vol. 46, 1996.
2. K. K. Likharev, "Superconductors speed up computation," Phys. World, pp. 39-43, May 1997.
3. K. Gaj et al., "Toward a systematic design methodology for large multi-gigahertz rapid single flux quantum circuits," IEEE Trans. Appl. Superconduct., to be published.
4. M. Aoyagi et al., "Chip layout design of a Josephson LSI circuit for examining high-speed operability by using a standard cell automatic placement and routing technique," IEEE Trans. Appl. Superconduct., vol. 4, pp. 169-176, Sept. 1994.
5. M. Khalaf, S. Whiteley, and T. Van Duzer, "A computer-aided design framework for superconductor circuits," IEEE Trans. Appl. Superconduct., vol. 5, pp. 3341-3344, June 1995.
6. K. K. Likharev and V. K. Semenov, "RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems," IEEE Trans. Appl. Superconduct., vol. 1, pp. 3-28, 1991.
7. K. K. Likharev, "Rapid single-flux-quantum logic," in The New Superconductor Electronics, H. Weinstock and R. Ralston, Eds. Dordrecht: Kluwer, 1993, pp. 423-452.
8. S. V. Polonsky et al., "New RSFQ circuits," IEEE Trans. Appl. Superconduct., vol. 3, pp. 2566-2577, 1993.
9. S. V. Polonsky, V. K. Semenov, and A. F. Kirichenko, "Single flux, quantum B flip-flop and its possible applications," IEEE Trans. Appl. Superconduct., vol. 4, pp. 9-18, 1994.
10. V. K. Semenov, Yu. Polyakov, and D. Schneider, "Preliminary results on the analog-to-digital converter based on RSFQ logic," in CPEM Conf. Dig. Suppl., Braunschweig, Germany, June 1996, pp. 15-16.
11. O. A. Mukhanov, P. D. Bradley, S. B. Kaplan, S. V. Rylov, and A. F. Kirichenko, "Design and operation of RSFQ circuits for digital signal processing," in Proc. 5th Int. Superconductivity Electron. Conf., Nagoya, Japan, Sept. 1995, pp. 27-30.
12. Q. P. Herr et al., "Design and low speed testing of a four-bit RSFQ multiplier-accumulator," IEEE Trans. Appl. Superconduct., vol. 7, pp. 3168-3171, 1997.
13. O. A. Mukhanov, "RSFQ 1024-bit shift register for acquisition memory," IEEE Trans. Appl. Superconduct., vol. 3, pp. 3102-3113, Dec. 1993.
14. A. M. Herr, C. A. Mancini, N. Vukovic, M. F. Bocko, and M. J. Feldman, "High-speed operation of a 64-bit circular shift register," IEEE Trans. Appl. Superconduct., vol. 8, pp. 120-124, Sept. 1998.
15. S. R. Whiteley, "Josephson junctions in SPICE3," IEEE Trans. Mag., vol. 27, no. 2, pp. 2902-2905, Mar. 1991.
16. S. V. Polonsky, V. K. Semenov, and P. N. Shevchenko, "PSCAN: Personal superconductor circuit analyzer," Superconduct. Sci. Technol., vol. 4, pp. 667-670, 1991.
17. Q. P. Herr and M. J. Feldman, "Multiparameter optimization of RSFQ circuits using the method of inscribed hyperspheres," IEEE Trans. Appl. Superconduct., vol. 5, pp. 3337-3340, June 1995.
18. P. I. Bunyk and S. V. Rylov, "Automated calculation of mutual inductance matrices of multilayer superconductor integrated circuits," Ext. Abs. ISEC, p. 62, 1993.
19. A. Krasniewski, "Logic simulation of RSFQ circuits," IEEE Trans. Appl. Superconduct., vol. 3, pp. 33-38, Mar. 1993.
20. K. Gaj, C.-H. Cheah, E. G. Friedman, and M. J. Feldman, "Functional modeling of RSFQ circuits using Verilog HDL," IEEE Trans. Appl. Superconduct., vol. 7, pp. 3151-3154, June 1997.
21. V. Adler, K. Gaj, D. K. Brock, C.-H. Cheah, and E. G. Friedman, "A Cadence-based design environment for single flux quantum circuits," IEEE Trans. Appl. Superconduct., vol. 7, pp. 3294-3297, June 1997.
22. H. Toepfer, T. Harnisch, J. Kunert, S. Lange, and H. F. Uhlmann, "Formal description of the functional behavior of RSFQ logic circuits for design and optimization purposes," IEEE Trans. Appl. Superconduct., vol. 7, pp. 3630-3633, June 1997.
23. S. Polonsky, P. Shevchenko, A. Kirichenko, D. Zinoviev, and A. Rylyakov, "PSCAN'96: New software for simulation and optimization of complex RSFQ circuits," IEEE Trans. Appl. Superconduct., vol. 7, pp. 2685-2689, June 1997.
24. V. K. Semenov, Y. A. Polyakov, and D. Schneider, "Implementation of oversampling analog-to-digital converter based on RSFQ logic," Ext. Abs. ISEC, pp. 41-43, 1997.
25. Proc. HTMT Project Meeting, Univ. Delaware, July 21, 1997.
26. Hybrid Technology Multithreaded Architecture Project Web Page. Available at http://www.cacr.caltech.edu/HTMT.
27. D. L. Miller, J. X. Przybysz, A. H. Worsham, and A. H. Miklich, "Superconducting sigma-delta analog-to-digital converters," Ext. Abs. ISEC, pp. 38-40, 1997.
28. O. A. Mukhanov and S. V. Rylov, "Time-to-digital converters based on RSFQ digital counters," IEEE Trans. Appl. Superconduct., vol. 7, pp. 2669-2672, June 1997.
29. A. F. Kirichenko, O. A. Mukhanov, and S. V. Rylov, "Superconducting time-to-digital converters," Ext. Abs. ISEC, pp. 34-37, 1997.
30. V. K. Semenov, Y. A. Polyakov, and A. Ryzhikh, "Decimation filters based on RSFQ logic/memory cells," Ext. Abs. ISEC, pp. 344-346, 1997.
31. "Petaflops at SUNY stony brook," web page. Available at http://gamayun. physics.sunysb.edu/RSFQ/Research/PetaFLOPs.
32. T. Sterling, P. Messina, and P. H. Smith, Enabling Technologies for Peta(FL)OPS Computing. Cambridge, MA: MIT, 1995.
33. S. Whiteley, JSPICE3 - User's Manual.
34. Hypres Niobium Process Flow and Design Rules, Hypres, Inc., 175 Clearbrook Road, Elmsford, NY 10523 USA.
35. K. Gaj, Q. P. Herr, and M. J. Feldman, "Analysis of timing requirements for basic RSFQ cells," presented at the Applied Superconductivity Conf., Oct. 1994. Available http://www.ee. rochester.edu/users/sde/research/publications/asc94.
36. K. Gaj, E. G. Friedman, and M. J. Feldman, "Timing of multi-gigahertz rapid single flux quantum digital circuits," J. VLSI Signal Processing, vol. 9, pp. 247-276, 1997.
37. K. Gaj, "Survey of SDE design tools." Available on the web under http://www.ee.rochester.edu/users/sde/cad/survey.html.
38. H. Toepfer, H. Uhlmann, M. Knoll, H. Thiele, and M. Selent, "Design tools for parameter determination and simulation of integrated Josephson structures," IEEE Trans. Appl. Superconduct., vol. 5, pp. 3345-3348, 1995.
39. Odintsov, V. K. Semenov, and Zorin, "Specific problems of numerical analysis of the Josephson junction circuits," IEEE Trans. Mag., vol. 23, pp. 763-766, 1987.
40. O. Mukhanov, V. K. Semenov, and K. K. Likharev, "Ultimate performance of the RSFQ logic circuits," IEEE Trans. Mag., vol. 23, pp. 759-762, 1987.
41. M. Jeffery, private communication.
42. J. Satchell, "Stochastic simulation of SFQ logic," IEEE Trans. Appl. Superconduct., vol. 7, pp. 3315-3318, June 1997.
43. H. Toepfer, T. V. Filippov, and H. F. Uhlmann, "RSFQ cells: Transient noise simulations," Ext. Abs. ISEC, pp. 317-319, 1997.
44. D. K. Brock, private communication.
45. C. Hamilton and K. Gilbert, "Margins and yield in single flux quantum logic,"IEEE Trans. Appl. Superconduct., vol. 1, pp. 157-163, Dec. 1991.
46. J. Satchell, private communication.
47. Q. P. Herr, "Bit errors and yield optimization in superconducting digital single-flux-quantum electronics," Ph.D. dissertation, Univ. Rochester, 1997.
48. Q. Herr and K. Gaj, MALT Reference Manual. Available http://www.ee.rochester.edu/users/sde/research/software/malt/malt. reference.guide.html.
49. T. Harnisch and H. F. Uhlmann, "Application of different design centering methods for yield optimization of cryoelectronic circuits," Applied Superconductivity Inst. Phys. Conf., 1995, pp. 1717-1720.
50. T. Harnisch, J. Kunert, H. Toepfer, and H. F. Uhlmann, "Design centering methods for yield optimization of cryoelectronic circuits," IEEE Trans. Appl. Supercond., vol. 7, pp. 3434-3437, June 1997.
51. R. Koch and W. Benzing, "Multi-dimensional parameter optimization for RSFQ circuit design," Ext. Abs. ISEC, pp. 305-307, 1997.
52. S. Director and G. Hachtel, "The simplicial approximation approach to design centering," IEEE Trans. Circ. Syst., vol. 27, pp. 363-372, July 1977.
53. S. Director, W. Maly, and A. Strojwas, VLSI Design for Manufacturing: Yield Enhancement. Boston, MA: Kluwer, 1990.
54. A. V. Rylyakov and S. V. Polonsky, "All-digital 1-bit RSFQ autocorrelator for radioastronomy applications: Design and experimental results," IEEE Trans. Appl. Superconduct., Appendix, vol. 8, pp. 14-19, Mar. 1998.
55. EDIF WWW Home Page at http://www.edif.org/index.html.
56. W. H. Chang, "The inductance of a superconducting strip transmission line," J. Appl. Phys., vol. 50, no. 12, pp. 8129-8134, Dec. 1979.
57. M. J. Feldman, "Inductance calculation Rodeo, 1996-1997." Available on the web at http://www.ee.rochester.edu/users/sde/research/projects/ Inductance/survey.html.
58. B. Guan, M. J. Wengler, P. Rott, and M. J. Feldman, "Inductance estimation for complicated superconducting thin film structures with a finite segment method," IEEE Trans. Appl. Superconduct., vol. 7, pp. 2776-2779, June 1997.
59. A. R. Kerr, "Surface impedance of superconductors and normal conductors in EM simulators," Electronics Division Internal Rep. no. 302, National Radio Astronomy Observatory, Charlottesville, VA, Feb. 19, 1996.
60. Z. Du, S. R. Whiteley, and T. Van Duzer, "Inductance calculation of 3D superconducting structures," Ext. Abs. ISEC, pp. 293-295, 1997.
61. P. H. Xiao, E. Charbon, A. Sangiovanni-Vincentell, T. Van Duzer, and S. R. Whiteley, "INDEX: An inductor extractor for superconducting circuits," IEEE Trans. Appl. Superconduct., vol. 3, pp. 2629-2632, Mar. 1993.
62. G. Hildebrandt and F. H. Uhlmann, "Inductance calculation for integrated superconducting structures by minimizing free energy," IEEE Trans. Appl. Superconduct., vol. 5, pp. 2766-2769, June 1995.
63. T. Nakazato and Y. Okabe, "Inductance computation of microscopic superconducting loop," IEEE Trans. Appl. Superconduct., vol. 7, pp. 3626-3629, June 1997.
64. M. M. Khapaev, "Extraction of inductances of a multi-superconductor transmission line," Superconduct. Sci. Technol., vol. 9, pp. 729-733, 1996.
65. _, "Extraction of inductances of plane thin film superconducting circuits," Superconduct. Sci. Technol., vol. 10, pp. 389-394, 1997.
66. P. Bunyk, A. Y. Kidiyarova-Shevchenko, and P. Litskevitch, "RSFQ microprocessor: New design approaches," IEEE Trans. Appl. Superconduct., Appendix, vol. 7, pp. 2697-2704, June 1997.
67. Standard 1076-1993, IEEE Standard VHDL Language Reference Manual, IEEE, 1994.
68. IEEE 1364 Standard, Verilog Hardware Description Language Reference Manual (LRM).
69. D. Perry, VHDL. New York: McGraw-Hill, 1991.
70. S. Palnitkar, Verilog HDL - A Guide to Digital Design and Synthesis. Englewood Cliffs, NJ: Prentice-Hall, 1996.
71. A. M. Dewey, Analysis and Design of Digital Systems with VHDL. New York: PWS, 1997.
72. J. R. Armstrong, Chip-Level Modeling with VHDL. Englewood Cliffs, NJ: Prentice-Hall, 1989.
73. U. Golze, VLSI Chip Design with the Hardware Description Language VERILOG. New York: Springer-Verlag, 1996.
74. D. Pellerin and D. Taylor, VHDL Made Easy! Englewood Cliffs, NJ: Prentice Hall, 1997.
75. P. Ashenden, The VHDL Cookbook. Available at ftp://bears.ucsb.edu/ pub/VHDL/comp.lang.vhdl.
76. K. Gaj, Q. P. Herr, and M. J. Feldman, "Parameter variations and synchronization of RSFQ circuits," Applied Superconductivity Conf, Institute of Physics, Bristol, U.K., 1995, Conf. Series #148, pp. 1733-1736.
77. K. Gaj, E. G. Friedman, M. J. Feldman, and A. Krasniewski, "A clock distribution scheme for large RSFQ circuits," IEEE Trans. Appl. Superconduct., vol. 5, pp. 3320-3324, 1995.
78. K. Gaj, "Timing of large RSFQ circuits," collection of slides available at http://www.ee.rochester.edu/users/sde/research/projects/rsfq/timing/title. html.
79. Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer, "Data-driven self-timed RSFQ digital integrated circuit and system," IEEE Trans. Appl. Superconduct., vol. 7, 1997.
80. P. Patra, S. Polonsky, and D. Fussel, "Delay insensitive logic for RSFQ superconductor technology," III Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 1996, pp. 42-53.
81. C. A. Mead and L. A. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1987, p. 115.
82. S. M. Rubin, Computer Aids for VLSI Design. Reading, MA, Addison-Wesley, 1987, p. 275.
83. J. Satchell, "Margins and errors in SFQ circuits," Ext. Abs. ISEC, pp. 44-46, 1997.