Time redundant error correcting adders and multipliers

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 1992-November, Issue , 1992, Pages 247-256

  Hsu, Yuang Ming ^a   Swartzlander, Earl E ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; DEFECTS; ERROR CORRECTION; REDUNDANCY; VLSI CIRCUITS;

CORRECT ERROR; DUPLICATION WITH COMPARISON; ERROR-CORRECTING; HARDWARE COMPLEXITY; HARDWARE OVERHEADS; INFORMATION REDUNDANCIES; RE-COMPUTING; TIME REDUNDANCY;

FAULT TOLERANCE;

EID: 37249076538     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1992.224350     Document Type: Conference Paper

References (5)

1. B. W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, Addison-Wesley, 1989.
2. D. A. Reynolds and G. Metze, "Fault detection capabilities of alternating logic," IEEE Trans. Comput., Vol. C-27, pp. 1093-1098, 1978.
3. J. H. Patel and L. Y. Fung, "Concurrent error detection in ALU's by recomputing with shifted operands," IEEE Trans. Comput., Vol. C-31, pp. 589-595, 1982.
4. B. W. Johnson, "Fault-tolerant microprocessor-based systems," IEEE Micro, Vol. 4, No. 6, pp. 6-21, December 1984.
5. B. W. Johnson, J. H. Aylor, and H. H. Hana, "Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder," IEEE J. Solid-Slate Circuits. Vol. 23, pp. 208-215, 1988.