Fail-safe synchronization circuit for duplicated systems

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 412-417

  Kolonis, Eleftherios ^a   Nicolaidis, Michael ^a  

^a iRoC Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTUATORS; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; SYNCHRONIZATION; USER INTERFACES;

FAIL-SAFE SIGNALS; SAFETY CRITICAL SYSTEMS; SYNCHRONIZATION CIRCUIT;

TIMING CIRCUITS;

EID: 0035193912     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2001.966795     Document Type: Article

References (4)

1. Basic properties and a construction method for fail-safe logical systems
2. Fail-safe interfaces for VLSI: Theoretical foundations and implementation
3. ISIS: A fail-safe interface realised in smart power technology
4. On line detection of logic errors due to cross-talk, delay and transient faults