Efficient systematic error-correcting codes for semi-delay-insensitive data transmission

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 24-29

  Cheng, F C ^a   Ho, S L ^a  

^a TATUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; ERROR CORRECTION; NETWORK PROTOCOLS;

SEMI-DELAY-INSENSITIVE (SDI) DATA;

DATA COMMUNICATION SYSTEMS;

EID: 0035183795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Asynchronous comparison-based decoders for delay-insensitive codes
2. On balanced codes
3. Coding for delay-insensitive communication with partial synchronization
4. Coding for skew-tolerant parallel asynchronous communications
5. Practical design and performance evaluation of completion detection circuits
6. Parallel computations and delay-insensitive circuits
7. Asynchronous design methodologies: An overview
8. Efficient balanced codes
9. Membership test logic for delay-insensitive codes
10. Delay-insensitive codes - An overview