Asynchronous comparison-based decoders for delay-insensitive codes

IEEE Transactions on Computers

Volumn 47, Issue 7, 1998, Pages 802-811

  Akella, Venkatesh ^a,c   Vaidya, Nitin H ^b,c   Redinbo, G Robert ^a,c  

^a University of California Davis   (United States)

^b Department of Electrical and Computer Engineering   (United States)

^c IEEE   (United States)

Author keywords

Block codes; Delay insensitive codes; Delay insensitive communication; Self timed design

Indexed keywords

DECODING; ERROR CORRECTION; ERROR DETECTION; INFORMATION THEORY; LOGIC CIRCUITS; LOGIC DESIGN;

ASYNCHRONOUS LOGIC; DELAY INSENSITIVE CODES; DELAY INSENSITIVE COMMUNICATION;

BLOCK CODES;

EID: 0032121216     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.709380     Document Type: Review

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