Boolean formula-based branch prediction for future technologies

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2001, Pages 97-106

  Jiménez, Daniel A ^a   Hanson, Heather L ^b   Lin, Calvin ^a  

^a University of Texas at Austin   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; ENCODING (SYMBOLS); MICROPROCESSOR CHIPS;

ALPHA PREDICTORS;

PIPELINE PROCESSING SYSTEMS;

EID: 0035176194     PISSN: 1089795X     EISSN: None     Source Type: Journal    
DOI: 10.1109/PACT.2001.953291     Document Type: Article

References (28)

1. Clock rate versus ipc: The end of the road for conventional microarchitectures
2. Learning readonce formulas with queries
3. Architectural support for compiler-synthesized dynamic branch prediction strategies: Rationale and initial results
4. Branch prediction for free
5. Evidence-based static branch prediction using machine learning
6. Reducing branch costs via branch alignment
7. K7 challenges Intel
8. The YAGS branch prediction scheme
9. The impact of delay on the design of branch predictors
10. Dynamic branch prediction with perceptrons
11. The alpha 21264 microprocessor
12. The bi-mode branch predictor
13. Compiler synthesized dynamic branch prediction
14. Correlation and aliasing in dynamic branch predictors
15. The Agree predictor: A mechanism for reducing negative branch history interference
16. Variable length path branch prediction
17. A new technique for standby leakage reduction in high performance circuits
18. Two-level adaptive branch prediction
19. Near-optimal intraprocedural branch alignment
20. Static correlated branch prediction