Transistor performance: The impact of implant doping accuracy

Solid State Technology

Volumn 44, Issue 1, 2001, Pages 88-92

  Adibi, Babak ^a,c,d   Meniailenkov, Viktor ^b  

^a APPLIED MATERIALS INC   (United States)

^b Integrated Systems Engineering Inc   (United States)

^c UNIVERSITY OF SURREY   (United Kingdom)

^d IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIFFUSION; ELECTRIC CONDUCTIVITY; ION IMPLANTATION; LEAKAGE CURRENTS; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; SOFTWARE ENGINEERING; THRESHOLD VOLTAGE;

CONDUCTIVE IMPLANT; PARAMETRIC IMPLANT; THERMAL ANNEALING;

TRANSISTORS;

EID: 0035121103     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (6)

1. ITRS1999 at http://public.itrs.net/files/1999_SIA_Roadmap/FEP.pdf.
2. TCAD paper to be published by ISE at the December 2000 International Electron Devices Meeting.
3. Scott Thompson, Paul Packan, Mark T. Bohr, "MOS Scaling: Transistor Challenges for the 21st Century," Intel Corporation at: http://developer.intel.com/technology/itj/q31998/articles/art_3.htm
4. Private communication.
5. D. Kapila, et al., IEEE Trans. Semicon. Manufac., Vol. 12, pp. 457-461, 1999.
6. Amir Al-Bayati, et al., "Spike Anneals for Ultra-low Energy," European Semiconductor, p. 41, July 2000.