Terabit multiservice switch

IEEE Micro

Volumn 21, Issue 1, 2001, Pages 58-70

  Yun, Kenneth Y ^a,b,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Applied Micro Circuits Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; FIBER OPTIC NETWORKS; INTERFACES (COMPUTER); QUALITY OF SERVICE; RESPONSE TIME (COMPUTER SYSTEMS); ROUTERS; SEMICONDUCTOR LASERS; TELECOMMUNICATION TRAFFIC; TIME DIVISION MULTIPLEXING;

CYCLONE SWITCH; MULTITERABIT SWITCHING SPEED; PACKET SEGMENTATION; VERTICAL CAVITY SURFACE EMITTING LASER; WEIGHTED FAIR QUEUEING;

SWITCHING SYSTEMS;

EID: 0035104833     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.903062     Document Type: Article

References (9)

1. M. Shreedhar and G. Varghese, "Efficient Fair Queuing Using Deficit Round-Robin," IEEE Trans. Networking, vol. 4, no. 3, Jun. 1996, pp. 375-385.
2. A.K. Parekh and R.G. Gallager, "A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Single Node Case," IEEE/ACM Trans. Networking, vol. 1, no. 3, Jun. 1993, pp. 344-357.
3. K. Thompson, G.J. Miller, and R. Wilder, "Wide-Area Internet Traffic Patterns and Characteristics," IEEE Network, vol. 11, no. 6, Nov./Dec. 1997, pp. 10-23.
4. N. W. McKeown, Scheduling Algorithms for Input-Queued Cell Switches, doctoral dissertation, EECS Dept, Univ. of California, Berkeley, 1995.
5. M. Katavenis, S. Sidiropoulos, and S. Courcoubetis, "Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip," IEEE J. Selected Areas in Communications, vol. 9, no. 8, Oct. 1991, pp. 1265-1279.
6. S.J. Golestani, "A Self-Clocked Fair Queueing Scheme for Broadband Applications," Proc. IEEE INFOCOM 94, IEEE, Piscataway, N.J., 1994, pp. 636-646.
7. H.J. Chao et al., "Design of a Generalized Priority Queue Manager for ATM Switches," IEEE J. Selected Areas in Communications, vol. 15, no. 5, Jun. 1997, pp. 867-880.
8. K.W. James and K.Y. Yun, "A 40Gb/s Packet Switching Architecture with Fine-Grained Priorities," Proc. Eighth Int'l Conf. on Computer Communications and Networks, IEEE Press, Piscataway, N.J., 1999, pp. 148-153.
9. K.W. James and K.Y. Yun, "Supporting Quality of Service in a Terabit Switch," Proc. 19th IEEE Int'l Performance, Computing, and Communications Conf., IEEE Press, Piscataway, N.J., 2000, pp. 55-61.