A 40 Gb/s packet switching architecture with fine-grained priorities

Proceedings - 8th International Conference on Computer Communications and Networks, ICCCN 1999

Volumn , Issue , 1999, Pages 148-153

  James, Kevin W ^a   Yun, Kenneth Y ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; HARDWARE; NETWORK ARCHITECTURE; PACKET NETWORKS; QUEUEING THEORY; ROUTERS;

CONFLICT RESOLUTION; HARDWARE COMPLEXITY; HEAD OF LINE BLOCKING; INPUT QUEUED SWITCH; NOVEL ARCHITECTURE; PRIORITY LEVELS; PRIORITY QUEUES; SWITCHING ARCHITECTURES;

PACKET SWITCHING;

EID: 0343006269     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCCN.1999.805509     Document Type: Conference Paper

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