A 128×128 CMOS imager with 4×128 bit-serial column-parallel PE array

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 96-97+436

  Yamashita, H ^a   Sodini, C G ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; FUNCTION GENERATORS; IMAGE ANALYSIS; IMAGE QUALITY; PARALLEL PROCESSING SYSTEMS; SEMICONDUCTOR DEVICE MANUFACTURE;

COLUMN PARALLEL PROCESSING ARCHITECTURE;

IMAGE SENSORS;

EID: 0035058232     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. PASIC. A smart sensor for computer vision
2. An embeddable low power SIMD processor bank
3. A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output
4. A pixel parallel image processor using logic pitch-matched to dynamic memory