Multibit Δ Σ ADC with mixed-mode DAC error correction

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 1, Issue , 2001, Pages 280-283

  Kiss, Péter ^a   Moon, Un Ku ^a   Steensgaard, Jesper ^b   Stonick, John T ^a   Temes, Gábor C ^a  

^a Oregon State University   (United States)

^b Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRECTION CIRCUITS; DIGITAL FILTERING; ERROR-CORRECTION SCHEMES; MIXED MODE; MULTI-BITS; OVER SAMPLING RATIO; SWITCHED CAPACITOR;

ERROR CORRECTION; ADAPTIVE FILTERING; CAPACITORS; DIGITAL FILTERS; DIGITAL TO ANALOG CONVERSION; RESISTORS; SAMPLING; SWITCHING CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

CORRECTION CIRCUIT; OVERSAMPLING RATIOS;

EID: 0034998361     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921847     Document Type: Conference Paper

References (13)

1. M. Sarhang-Nejad and G. C. Temes, "A high-resolution multibit sigma-delta ADC with digital correction and relaxed amplifier requirements." IEEE J. Sol id-State Circuits, vol. 28, no. 6, pp. 648-660, June 1993. (Pubitemid 23685787)
2. R. T. Baird and T. S. Fiez, "A low oversampling ratio 14-b delta-sigma ADC with self-calibrated multibit DAC", IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 312-320, 1996.
3. C. Petrie and M. Miller, "A background calibration technique for multibit delta-sigma modulators", in Proc. IEEE Int. Symp. Circuits and Systems, May 2000, pp. II.29-II.32.
4. L. R. Carley, "A noise-shaping coder topology for 15+ bit converters", IEEE J. Solid-State Circuits, vol. SC-24, no. 4, pp. 267-273, April 1989.
5. R. T. Baird and T. S. Fiez, "Improved delta-sigma DAC linearity using data weighted averaging", in Proc. IEEE Int. Symp. Circuits and Systems, May 1995. vol. 1, pp. 13-16.
6. I. Galton, "Noise-shaping D/A converters for sigma-delta modulation", in Proc. IEEE Int. Symp. Circuits and Systems, May 1996, vol. 1, pp. 441-444.
7. T. Kwan, R. Adams, and R. Libert. "A stereo multibit sigmadelta DAC with asynchronous master-clock interface", IEEE J. Solid-State Circuits, vol. 31, no. 12. pp. 1881-1887, 1996. (Pubitemid 126530140)
8. U. Moon, J. Silva, J. Steensgaard, and G. C. Temes, "A switched-capacitor DAC with analog mismatch correction", in Proc. IEEE Int. Symp. Circuits and Systems, May 2000, vol. 4, pp. IV.421-IV.424.
9. E. Fogleman, I. Galton, W. Huff, and H. Jensen, "A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR", IEEE J. Solid-State Circuits, vol. 35. no. 3, pp. 297-307, March 2000. (Pubitemid 30588024)
10. P. Kiss, U. Moon, J. Steensgaard, J. T. Stonick, and G. C. Temes, "High-speed multibit delta-sigma ADCs with online digital error correction", Research report, Oregon State University, July 2000.
11. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing, Wiley, 1986.
12. B. Razavi, Principles of Data Conversion System Design, New York: IEEE Press, 1995.
13. P. Kiss. J. Silva, A. Wiesbauer, T. Sun, U. Moon, J. T. Stonick. and G. C. Temes, "Adaptive correction of analog errors in MASH ADCs-Part II. Correction using test-signal injection", IEEE Trans. Circuits and Systems II, vol. 47, no. 7, pp. 629-638, July 2000.