Hierarchical performance optimization for synthesis of linear analog systems

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 5, Issue , 2001, Pages 431-434

  Doboli, Alex ^a   Vemuri, Ranga ^b  

^a STONY BROOK UNIVERSITY   (United States)

^b University of Cincinnati   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH LEVEL SYNTHESIS; OPERATIONAL AMPLIFIERS; ERROR ANALYSIS; GAIN CONTROL; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; OPTIMIZATION; SYSTEMS ANALYSIS; VLSI CIRCUITS;

ANALOG DESIGN; ANALOG SYSTEMS; CIRCUIT GAIN; DESIGN CONSTRAINTS; DESIGN PARAMETERS; GAIN DISTRIBUTION; PERFORMANCE OPTIMIZATIONS; SILICON AREA;

HIERARCHICAL SYSTEMS; LINEAR SYSTEMS;

LINEAR ANALOG SYSTEMS; SLEW-RATES (SR);

EID: 0034997870     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2001.922077     Document Type: Conference Paper

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