Applying dynamic voltage stressing to reduce early failure rate

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2001, Pages 37-41

  Tsao, C Y ^a   Shiue, R Y ^a   Ting, C C ^a   Huang, Y S ^a   Lin, Y C ^a   Yue, J T ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; PROBES; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; ULSI CIRCUITS;

CHIP PROBING; DYNAMIC VOLTAGE STRESS; EARLY LIFE FAILURE RATE; TEST DURING BURN IN;

RANDOM ACCESS STORAGE;

EID: 0034995211     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Evaluation of early failure screening methods
2. A model relating wearout induced physical changes in thin oxides to the statistical description of breakdown
3. Thickness dependence of stress-induced leakage currents in silicon oxide
4. High field related thin oxide wearout and breakdown
5. Technique for determining a prudent voltage stress to improve product quality and reliability
6. Semiconductor defect reliability screening & modeling