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Volumn , Issue , 2001, Pages 1-6

Reliability degradation of high density DRAM cell transistor junction leakage current induced by band-to-defect tunneling under the off-state bias-temperature stress

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; ELECTRIC CURRENT MEASUREMENT; ELECTRON TUNNELING; JUNCTION GATE FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; MOSFET DEVICES; RELIABILITY; THERMAL STRESS;

EID: 0034979842     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (11)
  • 4
    • 0033331595 scopus 로고    scopus 로고
    • Impact of the two traps related leakage mechanism on the tail distribution of DRAM retention characteristics
    • (1999) IEDM Tech. Dig. , pp. 37
    • Ueno, S.1
  • 5
    • 0033332829 scopus 로고    scopus 로고
    • Statistical PN junction leakage model with trap level fluctuation for Tref (retention time)-oriented DRAM design
    • (1999) IEDM Tech. Dig , pp. 539
    • Kamohara, S.1
  • 6
    • 0034454826 scopus 로고    scopus 로고
    • Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time
    • (2000) IEDM Tech. Dig. , pp. 837
    • Saino, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.