SPICE sensitivity analysis of a bipolar test structure during process development

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2000, Pages 187-192

  Rankin, N ^a   Walton, A J ^a   McGinty, J ^a   Fallon, M ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; COMPUTER AIDED ANALYSIS; COMPUTER AIDED DESIGN; MICROELECTRONIC PROCESSING; OPTIMIZATION; PARAMETER ESTIMATION; PROCESS ENGINEERING; PRODUCT DEVELOPMENT; SENSITIVITY ANALYSIS;

BIPOLAR TEST STRUCTURE; PROCESS DEVELOPMENT; SOFTWARE PACKAGE SPICE;

INTEGRATED CIRCUIT TESTING;

EID: 0033720162     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)