Digital filter synthesis based on minimal signed digit representation

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 468-473

  Park, I C ^a   Kang, H J ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; MULTIPLYING CIRCUITS;

CANNONICAL SIGNED DIGITS (CSD); MINIMAL SIGNED DIGITS (MSD);

DIGITAL FILTERS;

EID: 0034857669     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378564     Document Type: Conference Paper

References (16)

1. Use of minimum adder multiplier blocks in FIR digital filters
2. Primitive operator digital filters
3. A polynomial-time algorithm for designing digital filters with power-of-two coefficients
4. Binary arithmetic
5. An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients
6. Efficient substitution of multiple constant multiplication by shifts and additions using iterative pairwise matching
7. Synthesis of multiplier-less FIR filters with minimum number of additions
8. Subexpression sharing in filters using canonic signed digit multipliers
9. A new method for conversion of a 2's complement to canonic signed digit number system and its representation
10. A new algorithm for elimination of common subexpressions
11. A simple processor core design for DCT/IDCT
12. Decomposition of binary integers into signed power-of-two terms