New benchmark for RESURF, SOI, and super-junction power devices

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2001, Pages 343-346

  Zingg, R P ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

DMOS; High voltage; Impact ionization; RESURF; Silicon limit; Silicon on insulator; Specific on resistance; Super junctions

Indexed keywords

CORRELATION METHODS; ELECTRIC RESISTANCE; INTEGRAL EQUATIONS; IONIZATION; MOS DEVICES; SILICON ON INSULATOR TECHNOLOGY;

SUPER-JUNCTION POWER DEVICES;

SEMICONDUCTOR JUNCTIONS;

EID: 0034835658     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Calculation of avalanche breakdown of Si p-n junctions
2. A review of RESURF technology
3. Realization of high BV>700V in thin SOI devices
4. A new generation of high voltage MOSFETs breaks the limit line or silicon
5. Mdmesh™: Innovative technology for high-voltage PowerMOSFETs
6. High-voltage devices on SOI
7. Wide bandgap semiconductor power electronics