Development of a lead free chip scale package for wireless applications

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 665-670

  Kripesh, Vaidyanathan ^a   Teo, Poi Siong ^a   Chong, Chai Tai ^a   Vishwanadam, Gautham ^a   Mui, Yew Cheong ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b Advanced Micro Devices (S) Pte Ltd   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

AGING OF MATERIALS; LEAD; METALLIZING; RELIABILITY; SEMICONDUCTING TIN COMPOUNDS; SHEAR STRENGTH; SOLDERING ALLOYS; THERMAL CYCLING; WETTING; WIRELESS TELECOMMUNICATION SYSTEMS;

EUTECTIC TIN LEAD; LEAD FREE SOLDERS; THERMAL AGING; UNDER BUMP METALLIZATION;

CHIP SCALE PACKAGES;

EID: 0034835457     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2001.927802     Document Type: Article

References (11)

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6. Void formation in flip chip solder bumps - Part-I
7. Void formation in flip chip solder bumps - Part-II
8. Formation, distribution and failure effect of voids in vapor phase soldered small solder volumes
9. Under bump metallization for lead free solders