Design and simulation of a pipelined decompression architecture for embedded systems

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2001, Pages 63-68

  Lekatsas, Haris ^a   Henkel, Jorg ^a   Wolf, Wayne ^b  

^a NEC LABORATORIES AMERICA   (United States)

^b PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA COMPRESSION; DIGITAL STORAGE; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS;

PIPELINED DECOMPRESSION ARCHITECHTURE;

PIPELINE PROCESSING SYSTEMS;

EID: 0034795520     PISSN: 10801820     EISSN: None     Source Type: Journal    
DOI: 10.1145/500001.500015     Document Type: Article

References (12)

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7. Code density optimization for embedded DSP processors using data compression techniques
8. A method for the construction of minimum-redundancy codes
9. Selective instruction compression for memory energy reduction in embedded systems