Cache-efficient memory layout of aggregate data structures

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2001, Pages 101-106

  Panda, Preeti Ranjan ^a   Semeria, Luc ^b   De Micheli, Giovanni ^c  

^a SYNOPSYS INC   (United States)

^b Clearwater Networks Inc   (United States)

^c STANFORD UNIVERSITY   (United States)

Author keywords

Data Cache; Data Layout; Embedded Processors

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); DATA STRUCTURES; EMBEDDED SYSTEMS; PROGRAM COMPILERS;

CACHE-EFFICIENT MEMORY LAYOUT;

CACHE MEMORY;

EID: 0034790789     PISSN: 10801820     EISSN: None     Source Type: Journal    
DOI: 10.1145/500001.500026     Document Type: Article

References (13)

1. Hardware-software co-synthesis of microcontrollers
2. Allocation of multiport memories for hierarchical data streams
3. Memory data organization for improved cache performance in embedded processor applications
4. Resolution of dynamic memory allocation and pointers for the behavioral synthesis from C
5. Resolution, optimization, and encoding of pointer variables for the behavioral synthesis from C
6. Memory management for embedded network applications
7. Efficient context-sensitive analysis for C programs