Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 5, Issue 2, 1997, Pages 161-174

  Nekili, Mohamed ^a   Bois, Guy ^a   Savaria, Yvon ^a,b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b IEEE

Author keywords

H tree; High speed clocking; Pipelining; Process variations; Skew

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; PIPELINE PROCESSING SYSTEMS; PROBABILISTIC LOGICS; TIMING CIRCUITS; TREES (MATHEMATICS);

HIGH SPEED CLOCKING; SKEW MODELING;

DIGITAL CIRCUITS;

EID: 0031163868     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.585214     Document Type: Article

References (21)

1. R. Comerford, "How DEC developed alpha," IEEE Spectrum, vol. 29, pp. 26-31, July 1992.
2. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
3. H. B. Bakoglu, J. T. Walker, and J. D. Meindl, "A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in ULSI & WSI circuits," in Proc. IEEE Int. Conf. Computer Design: VLSI in Computers, ICCD '86.
4. A. L. Fisher and H. T. Kung, "Synchronizing large VLSI processor arrays," IEEE Trans. Comput., vol. C-34, Aug. 1985.
5. M. Shoji, "Elimination of process-dependent clock skew in CMOS VLSI," IEEE J. Solid-State Circuits, vol. SC-21, Oct. 1986.
6. E. G. Friedman and S. Powell, "Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI," IEEE J. Solid-State Circuits, vol. SC-21, Apr. 1986.
7. S. D. Kugelmass and K. Steiglitz, "An upper bound on expected clock skew in synchronous systems," IEEE Trans. Comput., vol. C-39, pp. 1475-1477, Dec. 1990.
8. S. Dhar, M. A. Franklin, and D. F. Wann, "Reduction of clock delays in VLSI structures," in Proc. Int. Conf. Comput. Design (ICCD-84), Port Chester, NY, Oct. 8-11, 1984.
9. M. Repeta, "Fabrication et caractérization de MESFET sur des couches épitaxiales d'Arseniure de gallium," Thèse de M.ing Département de génie physique, Ecole Polytechnique de Montreal, Apr. 1987.
10. A. Afghahi and C. Svensson, "Calculation of clock path delay and skew in VLSI synchronous systems," in European Conf. Circuit Theory and Design IEE, London, England, 1989, Conf. Pub. 308, pp. 265-269.
11. P. D. Bassett, L. A. Glasser, and R. D. Rettberg, "Dynamic delay adjustment: A technique for high-speed asynchronous communication," in Proc. Fourth MIT Conf. 1987.
12. Y. Savaria, "Conception et vérification des circuits VLSI," editions of École Polytechnique de Montreal, 1988.
13. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
14. "Design rules and process parameters for the Northern Telecom CMOS4S process," David Brown and Andrew Scott, Canadian Microelectron. Corp., Rep. IC90-01, Feb. 8, 1990.
15. "HSPICE H9001," User's Manual Meta-Software 1990.
16. M. Nekili, G Bois, and Y. Savaria, "Deterministic skew modeling and high-speed clocking using logic-based and mixed H-trees within integrated systems," École Polytechnique de Montréal, Tech. Rep. EPM/RT 94/09, 1994.
17. W. J. Dally, A VLSI Architecture for Concurrent Data Structures. New York: Kluwer Academic, 1987.
18. D. C. Keezer and V. K. Jain, "Design and evaluation of wafer scale," in Proc. 1992 Conf. WSI, pp. 168-175.
19. M. Nekili and Y. Savaria, "Parallel regeneration of interconnections in VLSI & ULSI circuits," IEEE Int. Symp. Circ. Syst., Chicago, IL, May 3-6, 1993.
20. A. Pavasovic, A. G. Andreou, and G. R. Westgate, "Characterization of subthreshold MOS mismatch in transistors for VLSI systems," J. VLSI Sig. Proc., June 1994.
21. A. G. Andreau and K. A. Boahen, "Neural information processing II," in Analog VLSI, M. Ismail and T. Fiez, Eds. New York: McGraw-Hill, 1994.