Circuit clustering for delay minimization under area and pin constraints

Proceedings of the 1995 European Conference on Design and Test, EDTC 1995

Volumn , Issue , 1995, Pages 65-70

  Yang, Honghua ^a   Wong, D F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; LOGIC GATES; TIMING CIRCUITS;

BENCHMARK CIRCUIT; CHIP IMPLEMENTATION; CIRCUIT CLUSTERING; CIRCUIT DELAYS; CIRCUIT PARTITIONING; DELAY MINIMIZATION; DELAY MODELING; OPTIMAL DELAY;

CLUSTERING ALGORITHMS;

EID: 33746372654     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/edtc.1995.470418     Document Type: Conference Paper

References (8)

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