Test generation for path-delay faults in one-dimensional iterative logic arrays

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 326-335

  Abdulrazzaq, Nabil M ^a   Gupta, Sandeep K ^a  

^a University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; DATA STORAGE EQUIPMENT; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; MULTICHIP MODULES; ONE DIMENSIONAL;

HIGH SPEED MEMORIES; INTERCONNECTION PATTERN; ONE DIMENSIONAL ITERATIVE LOGIC ARRAYS; PATH DELAY FAULTS;

LOGIC CIRCUITS;

EID: 0034482663     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2000.894221     Document Type: Article

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