Partitioning algorithm to enhance VLSI testability

Proceedings of the Annual Southeast Conference

Volumn , Issue , 1998, Pages 121-129

  Shaer, Bassam ^a   Al Arian, Sami A ^a   Landis, David ^a  

^a UNIVERSITY OF MINNESOTA DULUTH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; LOGIC GATES; VLSI CIRCUITS;

PARTITIONING ALGORITHMS; PSEUDO EXHAUSTIVE TESTING METHODS;

COMBINATORIAL CIRCUITS;

EID: 0031683764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/275295.275315     Document Type: Conference Paper

References (15)