Pseudo-exhaustive testing of sequential circuits

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 109-112

  Shaer, Bassam ^a   Al Arian, Sami A ^a   Landis, David ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; DELAY CIRCUITS; DESIGN FOR TESTABILITY; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; VLSI CIRCUITS;

HARDWARE OVERHEAD; PARTITIONING ALGORITHM; PRIMARY INPUT CONES AND FANOUT VALUES; PSEUDO EXHAUSTIVE TESTING;

SEQUENTIAL CIRCUITS;

EID: 0033358212     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)