Implicit enumeration of strongly connected components and an application to formal verification

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 10, 2000, Pages 1225-1230

  Xie, Aiguo ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY SEQUENCES; COMPUTATIONAL METHODS; DATA STRUCTURES; DECISION THEORY; FINITE AUTOMATA; FORMAL LOGIC; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; MATRIX ALGEBRA;

ADJACENCY MATRIX; BINARY DECISION DIAGRAM; FORMAL VERIFICATION; STRONGLY CONNECTED COMPONENTS;

COMPUTER AIDED DESIGN;

EID: 0034296833     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.875347     Document Type: Article

References (12)

1. R. H. Hardin, R. P. Kurshan, S. K. Shukla, and M. Y. Vardi, "A new heuristic for bad cycle detection using BDDs," in Proc. Int. Workshop Computer-Aided Verification, 1997, pp. 268-278.
2. A. V. Aho, J. E. Hopcroft, and J. D. Ullman, The Design and Analysis of Computer Algorithms. Reading, MA: Addison-Wesley, 1974.
3. R. E. Tarjan, "Depth first search and linear graph algorithms," ACM J. Computing, vol. 1, no. 2, 1972.
4. R. E. Bryant, "Graph-based algorithm for boolean function munipulation," IEEE Trans. Comput., vol. C-35, Aug. 1986.
5. G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Markovian analysis of large FSMs," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1479-1493, Dec. 1996.
6. G. Hasteer, A. Mathur, and P. Banerjee, "An implicit algorithm for finding steady states and its applications to FSM verifcation," in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 611-614.
7. A. Xie and P. A. Beerel, "Efficient state classification of finite state Markov chains," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1334-1338, Dec. 1998.
8. V. Singhal, "Design Replacements for Sequential Circuits," Ph.D. dissertation, Univ. California, Berkeley, 1996.
9. S. Qadeer, R. K. Brayton, V. Singhal, and C. Pixley, "Latch redundancy removal without global reset," in Proc. Int. Conf. Computer Design (ICCD), Oct. 1996, pp. 432-439.
10. E. A. Emerson and C. L. Lei, "Efficient model checking in fragments of the prepositional modal mu-calculus," in Proc. LICS 1986, 1986, pp. 267-278.
11. J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill, "Symbolic model checking for sequential circuit verification," IEEE Trans. Computer-Aided Design, vol. 13, pp. 401-424, Apr. 1994.
12. R. K. Brayton, G. D. Hachtel, A. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S.-T. Cheng, S. Edwards, S. Kharti, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. Villa, "VIS: A system for verfication and synthesis," in Proc. Int. Conf. Computer-Aided Verification, 1996, pp. 428-432.