Latch redundancy removal without global reset

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 432-439

  Qadeer, Shaz ^a   Brayton, Robert K ^a   Singhal, Vigyan ^a   Pixley, Carl ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL SWITCHING; FINITE AUTOMATA; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; OPTIMIZATION; REDUNDANCY; SEQUENTIAL SWITCHING; STATE ASSIGNMENT;

FINITE STATE MACHINES (FSM); LATCH REDUNDANCY REMOVAL;

FLIP FLOP CIRCUITS;

EID: 0030422278     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)