Low-cost single-layer clock trees with exact zero Elmore delay skew

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 213-218

  Kahng, Andrew B ^a   Tsao, Chung Wen Albert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; TREES (MATHEMATICS);

EMBEDDING RULES; MERGING SEGMENTS; PARTITIONING RULES; ZERO SKEW TREE;

LOGIC CIRCUITS;

EID: 0028712930     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (16)