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Volumn 147, Issue 4, 2000, Pages 237-242

Sensitivity study and improvements on a nonlinear resistive-type neuron circuit

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE NETWORKS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; NONLINEAR NETWORKS; RESISTORS; VLSI CIRCUITS;

EID: 0034250277     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20000237     Document Type: Article
Times cited : (14)

References (12)
  • 2
    • 0024771475 scopus 로고
    • 'Pattern classification using neural networks'
    • LIPPMANN, R.P.: 'Pattern classification using neural networks' IEEE Commun. Mag., 1989, 27, (11), pp. 47-64
    • (1989) IEEE Commun. Mag. , vol.27 , Issue.11 , pp. 47-64
    • Lippmann, R.P.1
  • 3
    • 0029244593 scopus 로고
    • 'Recognition of handwritten numerals with multiple feature and multistage classifier'
    • CAO, J., SHRIDHAR, M., and AHMADI, M.: 'Recognition of handwritten numerals with multiple feature and multistage classifier' J. Pattern Recognit., 1995, 28, (2), pp. 153-163
    • (1995) J. Pattern Recognit. , vol.28 , Issue.2 , pp. 153-163
    • Cao, J.1    Shridhar, M.2    Ahmadi, M.3
  • 4
    • 0026866736 scopus 로고
    • 'Application of the ANNA neural network chip to high-speed character recognition'
    • SACKINGER, E., BÖSER, B.E., BROMLEY, J., LECUN, Y., and JACKEL, L.D.: 'Application of the ANNA neural network chip to high-speed character recognition' IEEE Trans. Neural Nein:. 1992, 3, (3), pp. 498-505
    • (1992) IEEE Trans. Neural Nein:. , vol.3 , Issue.3 , pp. 498-505
    • Sackinger, E.1    Böser, B.E.2    Bromley, J.3    Lecun, Y.4    Jackel, L.D.5
  • 5
    • 0029267941 scopus 로고
    • 'The selection of weight accuracies for madalines'
    • PICHE, S.W.: 'The selection of weight accuracies for madalines' IEEE Traits. Neural New., 1995, 6, (2), pp. 432-445
    • (1995) IEEE Traits. Neural New. , vol.6 , Issue.2 , pp. 432-445
    • Piche, S.W.1
  • 6
    • 0027555961 scopus 로고
    • 'Design and characterization of analog VLSI neural network modules'
    • GOWDA, S.M., SHEU, B.J., CHOI,J., HWANG, C, and CABLE, J.S.: 'Design and characterization of analog VLSI neural network modules' IEEEJ. Solid-State Circuits, 1993,28, (3), pp. 301-311
    • (1993) IEEEJ. Solid-State Circuits , vol.28 , Issue.3 , pp. 301-311
    • Gowda, S.M.1    Sheu, B.J.2    Choi, J.3    Hwang, C.4    Cable, J.S.5
  • 10
    • 34250842470 scopus 로고
    • 'A multiple-input OTA circuit for neural networks'
    • REDD, R.D., and GEIGER, R.L.: 'A multiple-input OTA circuit for neural networks' IEEE Traits. Circuits Syst., 1989, 36, (5), pp. 767769
    • (1989) IEEE Traits. Circuits Syst. , vol.36 , Issue.5 , pp. 767769
    • Redd, R.D.1    Geiger, R.L.2
  • 12
    • 0031361413 scopus 로고    scopus 로고
    • 'A self-scaling neural hardware structure that reduces the effect of some implementation errors'
    • Amelia Island, Florida, Sept. 1997, in 'Neural networks for signal processing VII'
    • DJAHANSHAHI, H., AHMADI, M., JULLIEN, G.A., and MILLER, W.C.: 'A self-scaling neural hardware structure that reduces the effect of some implementation errors'. Proceedings of the 1997 IEEE Workshop (NNSP'97), Amelia Island, Florida, Sept. 1997, pp. 588-597 (in 'Neural networks for signal processing VII')
    • Proceedings of the 1997 IEEE Workshop (NNSP'97) , pp. 588-597
    • Djahanshahi, H.1    Ahmadi, M.2    Jullien, G.A.3    Miller, W.C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.