A 5.3GHz programmable divider for HiPerLAN in 0.25μm CMOS

European Solid-State Circuits Conference

Volumn , Issue , 1999, Pages 142-145

  Krishnapura, N ^a   Kinget, P ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

D FLIP-FLOPS; FREQUENCY DIVIDERS; M-TECHNOLOGIES; PHASE SWITCHING; PROGRAMMABILITY; PROGRAMMABLE DIVIDER; RESIDUAL PHASE NOISE; SINGLE-ENDED INPUT;

EID: 77956024833     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. J. Craninckx and M. S. J. Steyaert, "A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-m CMOS", IEEE Journal of Solid State Circuits, vol. 31, no. 7, pp. 890-897, July 1996.
3. M. H. Perrott, Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers, PhD thesis, Massachusetts Institute of Technology, Sep. 1997.
4. J. Yuan and C. Svensson, "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989.
5. B. Razavi et al., "Design of High-Speed, Low-Power Frequency Dividers and Phase Locked Loops in Deep Submicron CMOS", IEEE Journal of Solid State Circuits, vol. 30, no. 2, pp. 101-109, Feb. 1995.
6. W. F. Egan, "Modeling Phase Noise in Frequency Dividers", IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, vol. 37, no. 4, pp. 307-315, Jul. 1990.