In process stress analysis of flip chip assemblies during underfill cure

American Society of Mechanical Engineers, EEP

Volumn 22, Issue , 1997, Pages 7-14

  Palaniappan, Prema ^a   Baldwin, Daniel F ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; CURING; ELECTRONICS INDUSTRY; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; PRINTED CIRCUIT BOARDS; RESIDUAL STRESSES; STRESS ANALYSIS;

FLIP CHIP ON LOW COST CIRCUIT BOARDS (FCOB); UNDERFILL CURES;

FLIP CHIP DEVICES;

EID: 0031358874     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)