High performance fully selective double recess InAlAs/InGaAs/InP HEMT's

IEEE Electron Device Letters

Volumn 21, Issue 7, 2000, Pages 335-337

  Wang, S C ^a   Liu, J S ^a   Hwang, K C ^a   Kong, W ^a   Tu, D W ^a   Ho, P ^a,b   Mohnkern, L ^a   Nichols, K ^a   Chao, P C ^a  

^a LOCKHEED MARTIN   (United States)

^b Global Communication Semiconductors   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; ELECTRIC BREAKDOWN; ETCHING; GATES (TRANSISTOR); SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING INDIUM PHOSPHIDE; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DEVICE TESTING; SILICON WAFERS; TRANSCONDUCTANCE; TUNING;

GATE DRAIN BREAKDOWN VOLTAGE; POWER ADDED EFFICIENCY; POWER MEASUREMENTS;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0034217278     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.847372     Document Type: Article

References (9)

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