New and improved borderless contact (BLC) structure for high-performance Ti-salicide in sub-quarter micron CMOS devices

IEEE Electron Device Letters

Volumn 21, Issue 7, 2000, Pages 344-346

  Liu, Wen Chau ^a   Thei, Kong Beng ^a   Wang, Wei Chou ^a   Pan, Hsi Jen ^a   Wuu, Shou Gwo ^b   Lei, Ming Ta ^b   Wang, Chung Shu ^b   Cheng, Shiou Ying ^c  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c ORIENTAL INSTITUTE OF TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; ELECTRIC CONTACTS; ETCHING; LEAKAGE CURRENTS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS; SILICON COMPOUNDS; THERMODYNAMIC STABILITY; TITANIUM;

BORDERLESS CONTACT STRUCTURE; DOUBLE IMPLANT STRUCTURE; SHALLOW TRENCH ISOLATION; SILICIDE; SUB QUARTER MICRON DEVICES;

MOS DEVICES;

EID: 0034217212     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.847375     Document Type: Article

References (10)

1. C. K. Lau et al., "Titanium disilicide self-aligned source/drain+gate technology," in IEDM Tech. Dig., 1982, pp. 714-716.
2. B. Davari et al., "A high-performance 0.25-μm CMOS technology - II: Technology," IEEE Trans. Electron Devices, vol. 39, pp. 967-974, Apr. 1992.
3. Y. Taur et al., "High performance 0.1 μm CMOS devices with 1.5 V power supply," in IEDM Tech. Dig., 1993, pp. 127-130.
4. I. Sakai et al., "A new salicide process (PASET) for sub-half micron CMOS," in Proc. Symp. VLSI Technology, 1992, pp. 66-67.
5. S. Subbanna, T. Lii, and G. Shaidi, "A novel borderless contact/interconnect technology using aluminum oxide etch stop for high performance SRAM and logic," in IEDM Tech.Dig. , 1993, pp. 441-444.
6. M. Gallagher, C. Ebel, G. MacDougall, and T. Weeks, "A novel, borderless metal-to-diffusion contact technique," Proc. IEEE SEMI, pp. 13-15, 1995.
7. B. Descouts et al., "Characterization of silicon nitride films for borderless contact applications," in Proc. VMIC Conf., 1998, pp. 640-641.
8. T," IEEE Electron Device Lett., vol. 18, Dec. 1997.
9. C. T. Huang, T. F. Lei, C. H. Chu, and S. H. Shvu, "The influence of Ge-implantation on the electrical characteristics of the ultra-shallow junction formed by using silicide as a diffusion source," IEEE Electron Device Lett., vol. 17, Mar. 1996.
10. 2 layer," IEEE Trans. Electron Devices, vol. 44, pp. 526-534, Apr. 1997.