Fabrication of MOS-integrated metallic single electron memories

Microelectronic Engineering

Volumn 53, Issue 1, 2000, Pages 265-268

  Pepin A ^a   Vieu, C ^a   Launois, H ^a   Rosmeulen, M ^b   Van Rossum, M ^b   Mueller, H O ^c   Williams, D ^c   Mizuta, H ^c   Nakazato, K ^c  

^a Lab Microstruct and Microelectron   (France)

^b IMEC   (Belgium)

^c HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON BEAM LITHOGRAPHY; MICROELECTRONIC PROCESSING; MORPHOLOGY; MOSFET DEVICES; SEMICONDUCTING SILICON; TUNNEL JUNCTIONS;

LATERAL SINGLE ELECTRON MEMORY; MEMORY NODE; MULTIPLE TUNNEL JUNCTION; THERMAL EVAPORATION;

SEMICONDUCTOR STORAGE;

EID: 0034205567     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(00)00312-9     Document Type: Article

References (7)

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