A Fast Single-Chip Implementation of 8192 Complex Point FFT

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 3, 1995, Pages 300-305

  Castelain, D ^b   Joanblan, C ^a   Senn, P ^a  

^a ORANGE LABS   (France)

^b Centre Commun d'Etudes de Télédiffusion et Télécommunications   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DEMODULATION; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK TOPOLOGY; FOURIER TRANSFORMS; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS; SIGNAL ENCODING; TELEVISION RECEIVERS; TELEVISION TRANSMISSION;

CONVERGENT BLOCK FLOATING POINT; INTERNAL RESULT SCALING TECHNIQUE; SPECTRAL EFFICIENCY LOSS;

VLSI CIRCUITS;

EID: 0029264398     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.364445     Document Type: Article

References (12)

1. M. Alard and R. Lasalle, “Principles of modulation and channel coding for digital broadcasting for mobile receivers,” presented at the ITU WARC–ORB Conf., Sept. 1988.
2. P. Duhamel and M. Vetterli, “Fast Fourier transform: A tutorial review and a state of the art,” Signal Process., no. 19, 1990.
3. J. W. Cooley and J. W. Tukey, “An algorithm for machine computation of complex Fourier series,” Math. Comput., vol. 19, 1965.
4. Bhatia, Furuta, and Ponce, “A quasi radix-16 FFT VLSI processor,” in Proc. IEEE ICASSP, July 1991.
5. O'Brien, Mather, and Holland, “A 200 MIPS single-chip IK FFT processor,” in Proc. ISCCC, Feb. 1989.
6. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975, pp. 600–614.
7. Swartzlander, Young, and Joseph, “A radix-4 delay commutor for fast Fourier transform processor implementation,” IEEE J. Solid-State Circuits, vol. SC-19, Oct. 1984.
8. Swartzlander, Jain, and Hikawa, “A radix-8 wafer scale FFT processor,” J. VLSI Signal Process., vol. 4 Jan. 1992.
9. G. Bi and E. V. Jones, “A pipelined FFT processor for word-sequential data,” IEEE Trans. Acoust., Speech, Signal Process., vol. 37, Dec. 1989.
10. C. Joanblanq, F. Rothan, and P. Senn, “A video delay line compiler,” in Proc. ISCAS, New Orleans, LA, May 1990.
11. Blankenship and Hofstetter, “Digital pulse compression via fast convolution,” IEEE Trans. Acoust. Speech, Signal Process., vol. ASSP-23, pp. 191–199, Apr. 1975.
12. Schirrmeister, Müller, Reventlow, Reimers, and Siebert, “A single chip solution for a high speed 128-point radix-2 FFT calculation,” in Proc. Int. Workshop HDTV'93, Ottawa, Canada, Oct. 1993.