Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 2, 1996, Pages 228-243

  Bhatia, Sandeep ^a   Jha, Niraj K ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROLLABILITY; ELECTRIC NETWORK ANALYSIS; ERRORS; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; GRAPH THEORY; HEURISTIC METHODS; MATHEMATICAL MODELS; OBSERVABILITY; OPTIMIZATION; SCANNING; SHIFT REGISTERS;

DELAY MINIMIZATION; DELAY OVERHEADS; PATH DELAY FAULT TESTING; SYNTHESIS FOR PARALLEL SCAN; TESTABILITY;

SEQUENTIAL CIRCUITS;

EID: 0030086551     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.486668     Document Type: Article

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