Fabrication and performance of selective HSG storage cells for 256 Mb and 1 Gb DRAM applications

IEEE Transactions on Electron Devices

Volumn 47, Issue 3, 2000, Pages 584-592

  Banerjee, Aditi ^a   Wise, Rick L ^a   Plumton, D L ^a   Bevan, Malcolm ^a   Pas, M F ^a   Crenshaw, D L ^a   Aoyama, Shintaro ^b   Mansoori, Majid M ^c  

^a TEXAS INSTRUMENTS   (United States)

^b TOKYO ELECTRON LTD   (Japan)

^c ASM AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITOR STORAGE; CHEMICAL VAPOR DEPOSITION; CURRENT DENSITY; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC MATERIALS; DYNAMIC RANDOM ACCESS STORAGE; LEAKAGE CURRENTS; MOS CAPACITORS;

CROWN CAPACITOR STORAGE CELLS; LOW PRESSURE CHEMICAL VAPOR DEPOSITION (LPCVD);

ELECTRIC BATTERIES;

EID: 0033877345     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.824734     Document Type: Article

References (5)

1. T. Kaga, M. Ohkura, F. Murai, N. Yokoyama, and E. Takeda, "Process and device technologies for 1 Gb dynamic random access memory cells," J. Vac. Sci. Technol. B, vol. 13, pp. 2329-2334, Nov./Dec. 1995.
2. M. Ino et al., "Rugged surface polycrystalline silicon film deposition and its application in a stacked dynamic random access memory capacitor electrode," J. Vac. Sci. Technol. B, vol. 14, pp. 751-756, Mar./Apr. 1996.
3. 3/W capacitor technology for 1 Gb DRAM," in IEDM Tech. Dig, vol. 3.4.1-3.4.4, 1993, pp. 49-52.
4. H. Watanabe, A. Sakai, T. Tatsumi, and T. Niino, "Hemispherical grain silicon for high density DRAM's," Solid State Technol., pp. 29-33, July 1992.
5. H. Watanabe et al, "Hemispherical grained Si formation on in situ phosphorous doped amorphous-Si electrode for 256 Mb DRAM's capacitor," IEEE Trans. Electron Devices, vol. 42, pp. 1247-1254, July 1995.