A thermal van der Pauw test structure

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 2, 2000, Pages 159-166

  Paul, Oliver ^a,b   Ruther, Patrick ^b   Plattner, Luca ^c   Baltes, Henry ^c  

^a IEEE   (Germany)

^b UNIVERSITY OF FREIBURG   (Germany)

^c ETH ZURICH   (Switzerland)

Author keywords

Sheet resistance; Test structure; Thermal conductivity; Thin film; Van der Pauw method

Indexed keywords

SHEET RESISTANCE; THERMAL VAN DER PAUW TEST STRUCTURE;

CMOS INTEGRATED CIRCUITS; CURRENT DENSITY; ELECTRIC CONDUCTORS; FINITE ELEMENT METHOD; INTEGRATED CIRCUIT TESTING; SEMICONDUCTING SILICON; THERMAL CONDUCTIVITY; THIN FILMS;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0033688061     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.843631     Document Type: Article

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