Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

Microelectronic Engineering

Volumn 50, Issue 1-4, 2000, Pages 487-493

  Motte, P ^a   Torres, J ^b   Palleau, J ^b   Tardif, F ^c   Demolliens, O ^c   Bernard, H ^a  

^a STMICROELECTRONICS   (France)

^b ORANGE LABS   (France)

^c CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITION REACTIONS; CONTAMINATION; COPPER; DIELECTRIC MATERIALS; ELECTRIC RESISTANCE MEASUREMENT; INTERCONNECTION NETWORKS; INTERDIFFUSION (SOLIDS); OPTIMIZATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING SILICON COMPOUNDS;

DIELECTRIC DEPOSITIONS; DUAL DAMASCENE INTERCONNECTION ARCHITECTURE; INTERLEVEL DIELECTRICS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033640330     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(99)00319-6     Document Type: Article

References (6)

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