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Volumn , Issue , 1999, Pages 178-187

Field programmable gate array based radar front-end digital signal processing

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; DISTRIBUTED COMPUTER SYSTEMS; FIR FILTERS; FREQUENCY DOMAIN ANALYSIS; RADAR; SIGNAL FILTERING AND PREDICTION; VLSI CIRCUITS;

EID: 0033488499     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (18)

References (15)
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  • 3
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    • Virtex 2.5 V field programmable gate arrays
    • Xilinx Publications.; 9 November; Version 1.1
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    • (1998) Advance Product Specification
  • 4
    • 0012208516 scopus 로고    scopus 로고
    • VLSI bit-level systolic array for radar front-end signal processing
    • Technical report, MIT Lincoln Laboratory
    • W. S. Song. "VLSI bit-level systolic array for radar front-end signal processing." Technical report, MIT Lincoln Laboratory.
    • Song, W.S.1
  • 5
    • 0023999553 scopus 로고
    • Efficient bit-level systolic array implementation of FIR and IIR digital filters
    • April
    • C.-L. Wang, C.-H. Wei, and S.-H. Chen. "Efficient bit-level systolic array implementation of FIR and IIR digital filters." IEEE Journal on Selected Areas in Communications, 6(3): 484-493, April 1988.
    • (1988) IEEE Journal on Selected Areas in Communications , vol.6 , Issue.3 , pp. 484-493
    • Wang, C.-L.1    Wei, C.-H.2    Chen, S.-H.3
  • 7
    • 0030349290 scopus 로고    scopus 로고
    • A guide to using field programmable gate arrays (FPGAs) for application-specific digital signal processing performance
    • In J. Schewel, P. M. Athanas, V. M. Bove, Jr., and J. Watson, editors; Boston, MA, 20-21 November; SPIE-The International Society for Optical Engineering. Proc. SPIE 2914
    • G. R. Goslin. "A guide to using field programmable gate arrays (FPGAs) for application-specific digital signal processing performance." In J. Schewel, P. M. Athanas, V. M. Bove, Jr., and J. Watson, editors, Proceedings High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, pages 321-331, Boston, MA, 20-21 November 1996. SPIE-The International Society for Optical Engineering. Proc. SPIE 2914.
    • (1996) Proceedings High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic , pp. 321-331
    • Goslin, G.R.1
  • 8
    • 0002549262 scopus 로고
    • Using xilinx FPGAs to design custom digital signal processing devices
    • 12 January
    • G. R. Goslin. "Using Xilinx FPGAs to design custom digital signal processing devices." In DSPX 1995 Technical Proceedings, page 595, 12 January 1995.
    • (1995) DSPX 1995 Technical Proceedings , pp. 595
    • Goslin, G.R.1
  • 9
    • 0030258994 scopus 로고    scopus 로고
    • Implement DSP functions in FPGAs to reduce cost and boost performance
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    • Goslin, G.R.1
  • 10
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    • A distributed arithmetic approach to designing scalable DSP chips
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  • 12
    • 0031222835 scopus 로고    scopus 로고
    • Low-area/power parallel FIR digital filter implementation
    • D. A. Parker and K. K. Parhi. "Low-area/power parallel FIR digital filter implementation." Journal of VLSI Signal Processing, 17:75-92, 1997.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.