Multi-mode scannable memory element for high test application efficiency and delay testing

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 15, Issue 1, 1999, Pages 87-97

  Sogomonyan, E S ^a   Singh, Adit D ^c,d   Goessel, M ^b,e  

^a TRAPEZNIKOV INSTITUTE OF CONTROL SCIENCES   (Russian Federation)

^b UNIVERSITY OF POTSDAM   (Germany)

^c University of Massachusetts   (United States)

^d INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^e Saxonian Academy of Sciences   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; SEQUENTIAL CIRCUITS;

MULTI-MODE SCANNABLE MEMORY ELEMENT; MULTIPLE INPUT SIGNATURE ANALYZER (MISA);

SEMICONDUCTOR DEVICE TESTING;

EID: 0033348668     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008328101088     Document Type: Article

References (20)

1. E.B. Eichelberger and T.W. Williams, "A Logic Design Structure for LSI Testing," Proc. 14th Design Automation Conf., June 1977, pp. 462-468.
2. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.
3. B. Koenemann, J. Mucha, and G. Zwiehoff, "Built-In Logic Block Observation Techniques," Proc. Int. Test Conf., 1979, pp. 37-41.
4. L.T. Wang and E.J. McCluskey, "Concurrent Built-In Logic Block Observer (CBILBO)," Int. Symp. on Circuit and Systems, 1986, Vol. 3, pp. 1054-1057.
5. A. Krasniewski and S. Pilarski, "Circular Self-Test Path: A Low-Cost BIST Technique for VLSI Circuits," IEEE Trans. on Comput.-Aided Des., Vol. 8, No. 1, pp. 46-55, Jan. 1989.
6. H. Fujiwara and A. Yamamoto, "Parity-Scan Design to Reduce the Cost of Test Application," Proc. Int. Test Conf., 1992, pp. 283-292.
7. M. Goessel and E.S. Sogomonyan, "A Parity-Preserving Multi-Input Signature Analyzer and Its Application for Concurrent Checking and BIST," Journal of Electronic Testing: Theory and Applications, No. 8, pp. 165-177, 1996.
8. J. Savir, "Scan Latch Design for Delay Test," Proc. Int. Test Conf., 1997, pp. 446-453.
9. B. Nadeau-Dostie, D. Burek, and A. Hassan, "Scan Bist: A Multifrequence Scan-Based BIST Method," IEEE Design and Test of Computers, Spring 1994, p. 716.
10. C. Girard, C. Landrault, V. Moreda, S. Pravossoudovitch, and A. Virazel, "A Bist structure to Test Delay Faults in a Scan Environment," Proc. 7th Asian Test Symp., 1998, pp. 435-439.
11. E.S. Sogomonyan, A.D. Singh, and M. Goessel, "A Multy-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing," Proc. 16th VLSI Test Symposium, April 1998, pp. 324-331.
12. K. Kim, D.S. Ha, and J.G. Tront, "On Using Signature Registers as Pseudorandom Pattern Generators in Built-in Self-Testing," IEEE Trans. on Comput.-Aided Des., Vol. 7, No. 8, pp. 919-928, Aug. 1988.
13. C.E. Stroud, "Automated BIST for Sequential Logic Synthesis," IEEE Des. and Test of Comput., pp. 22-32, Dec. 1988.
14. J.L. Avra and E.J. McCluskey, "Synthesizing for Scan Dependence in Built-In Self-Testable Designs," Proc. Int. Test Conf., 1993, pp. 734-743.
15. A. Pierzynska and S. Pilarsky, "Non-Robust versus Robust," Proc. Int. Test Conf., 1995, pp. 123-131.
16. H. Fijiwara, Logic Testing and Design for Testability, MIT Press, Cambridge, MA, 1985.
17. R.A. Frohwerk, "Signature Analysis: A New Digital Field Service Method," Hewlett-Packard Journal, Vol. 28, pp. 2-8, May 1977.
18. C.-Lin, Y. Zorian, and S. Bhawmik, "Intagration of Partial Scan and Built-In Self-Test," Journal of Electronic Testing: Theory and Applications, Vol. 7, Nos. 1-2, pp. 125-137, Aug. 1995.
19. K.-T. Cheng and C.-Lin, "Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST," Proc. Int. Test Conf., 1995, pp. 506-514.
20. H. Bleeker, P. van den Eijnden, and F. de Jong, Boundary-Scan Test. A Practical Approach, Kluwer Academic Publishers, 1993, p. 225.