Multi-mode scannable memory element for high test application efficiency and delay testing

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 324-331

  Sogomonyan, E S ^a   Singh, A D ^a   Goessel, M ^a  

^a TRAPEZNIKOV INSTITUTE OF CONTROL SCIENCES   (Russian Federation)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DESIGN FOR TESTABILITY; EFFICIENCY; ELECTRIC FAULT LOCATION; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS;

DELAY TESTING;

SEQUENTIAL CIRCUITS;

EID: 0032308952     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)