Original cabling conditions to insure balanced current during switching transitions between paralleled semiconductors

Conference Record - IAS Annual Meeting (IEEE Industry Applications Society)

Volumn 3, Issue , 1999, Pages 1757-1764

  Jeannin, P O ^a   Schanen, J L ^a   Clavel, E ^a  

^a LABORATOIRE D ELECTROTECHNIQUE DE GRENOBLE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CABLING CONDITIONS; ELECTRICAL CONSTRAINTS;

CHOPPERS (CIRCUITS); COMPUTER SIMULATION; DIFFERENTIAL EQUATIONS; ELECTRIC CURRENTS; ELECTRIC INDUCTORS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; RESISTORS; SWITCHING NETWORKS;

MOSFET DEVICES;

EID: 0033325834     PISSN: 01972618     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Kun Xing, Fred C. Lee, Dushan Boroyevich "Extraction of Parasitics within Wire-Bond IGBT Modules" APEC'98. pp497-503
2. H. Heeb, AE Ruehli "Three-Dimensionnal Interconnect Analysis Using Partial Element EFvalent Circuits" IEEE transactions on circuits and systems -1: fundamental theory and applications Vol 39 no 11, november 1992, pp974-982
3. S. Miyashita, S. Yoshiwatari, S. Kobayashi K. Sakurai "Advanced Technology for a New NPT-IGBT Module Design" IEEE-IAS 1998, St.Louis, pp1061-1066
4. E. Clavel. J. Rought. J.L. Schanen "Influence of the Cabling Geometry on Paralleled Diodes in a High Power Rectifier" IEEE-IAS 1996, San Diego, pp993-998.
5. D.A. Paice "Multiple Paralleling of Power Diodes" IEEE transactions on industrial electronics and control instrumentation, Vol. IECI-22, no 2, may 1975, pp151- 158.
6. E.Farjah, J.L.Schanen, J.Roudet, J.P.Ferrieux "Power mosfet modelling based on its behavior" ELECTRIMACS' Montréal&9 Juillet 93 pp461-466.