Retiming of latches for power reduction of DSP designs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1997, Pages 2168-2171

  Simon, S ^a   Schimpfle, C V ^a   Wroblewski, M ^a   Nossek, J A ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK SYNTHESIS; LINEAR PROGRAMMING; LOGIC GATES; MATHEMATICAL MODELS; PIECEWISE LINEAR TECHNIQUES; VLSI CIRCUITS;

LEVEL SENSITIVE REGISTERS; POWER REDUCTION;

FLIP FLOP CIRCUITS;

EID: 0030689211     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)