SCOPUS 정보 검색 플랫폼

Volumn 34, Issue 11, 1999, Pages 1564-1570

18-Mb, 12.3-Gb/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

(9) Zhao, Cangsang a Bhattacharya, Uddalak a Denham, Martin a Kolousek, Jim a Lu, Yi a Ng, Yong Gee a Nintunze, Novat a Sarkez, Kamal a Varadarajan, Hemmige D a,b

a INTEL CORPORATION (United States)

b Applied Micro Circuits Corporation (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; DATA TRANSFER; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; SENSITIVITY ANALYSIS; TRANSISTORS;

STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0033221318 PISSN: 00189200 EISSN: None Source Type: Journal
DOI: 10.1109/4.799864 Document Type: Article

Times cited : (5)

References (5)

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3
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5
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.