A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1758-1764

  Nakamura, Kazuyuki ^b,c,d,e   Takeda, Koichi ^b   Toyoshima, Hideo ^b   Noda, Kenji ^a,b   Ohkubo, Hiroaki ^b   Uchida, Tetsuya ^b   Shimizu, Toshiyuki ^b   Itani, Toshiro ^b   Tokashiki, Ken ^b   Kishimoto, Koji ^b  

^a IEEE

^b NEC CORPORATION   (Japan)

^c KYUSHU UNIVERSITY   (Japan)

^d Stanford University   (United States)

^e Institute of Electronics   (Japan)

Author keywords

Cache memories; CMOS memory integrated circuits; Integrated circuit interconnections; Integrated circuit noise; Random access memories; SRAM chips

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENCODING (SYMBOLS); GATES (TRANSISTOR); SPURIOUS SIGNAL NOISE;

INTEGRATED CIRCUIT INTERCONNECTIONS; PREFETCHED PIPELINE BURST SCHEME; SOURCE RESETTING SCHEME;

RANDOM ACCESS STORAGE;

EID: 0031271698     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641698     Document Type: Article

References (10)

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