SCOPUS 정보 검색 플랫폼

Electronics Letters

Volumn 35, Issue 21, 1999, Pages 1881-1883

Detailed calculation of vertical electric field in thin oxide MOSFETs

(2) Gennai, S a Iannaccone, G a

a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BAND STRUCTURE; CARRIER CONCENTRATION; COMPUTER SIMULATION; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); MATHEMATICAL MODELS; OXIDES; QUANTUM THEORY; SEMICONDUCTING SILICON; WAVE EQUATIONS;

POISSON EQUATION; SCHRODINGER EQUATION;

MOSFET DEVICES;

EID: 0033204372 PISSN: 00135194 EISSN: None Source Type: Journal
DOI: 10.1049/el:19991253 Document Type: Article

Times cited : (1)

References (3)

1
- 33646933858
- 1997
- 'The national technology roadmap for semiconductors' (Semiconductor Industry Association, San Jose, California, US, 1997)
- Association, T.N.¹ Jose, S.² California, U.S.³

2
- 0031122158
- 1997, 85, pp. 486-504
- TAUR, Y., BUCHANAN, D.A., CHEN, W., FRANK, D.J., ISMAIL, K.E., LO, S., SAI-HALASZ, G.A., VISWANATHAN, R.G., WAHN, H.C., WIND, S.J., and WONG, H.-S.: 'CMOS scaling into the nanometer regime', Proc. IEEE, 1997, 85, pp. 486-504
- BUCHANAN, D.A., CHEN, W., FRANK, D.J., ISMAIL, K.E., LO, S., SAI-HALASZ, G.A., VISWANATHAN, R.G., WAHN, H.C., WIND, S.J., and WONG, H.-S.: 'CMOS Scaling into the Nanometer Regime', Proc. IEEE
- Taur, Y.¹

3
- 0032028948
- 1998, ED-45, pp. 691-699
- MOMOSE, H.S., NAKAMURA, S., OHGURO, T., YOSHITOMI, T., MORIFUJI, E., KATSUMATA, Y., and IWAI, H.: 'Study of the manufacturing feasibility of 1.5nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide', IEEE Trans., 1998, ED-45, pp. 691-699
- NAKAMURA, S., OHGURO, T., YOSHITOMI, T., MORIFUJI, E., KATSUMATA, Y., and IWAI, H.: 'Study of the Manufacturing Feasibility of 1.5nm Direct-tunneling Gate Oxide MOSFETs: Uniformity, Reliability, and Dopant Penetration of the Gate Oxide', IEEE Trans.
- Momose, H.S.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.