A 200-MHz CMOS I/Q downconverter

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 46, Issue 6, 1999, Pages 808-810

  Yim, Darwin T S ^a   Ling, Curtis C ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; ELECTRIC FILTERS; INTEGRATED CIRCUIT LAYOUT; OSCILLATORS (ELECTRONIC); SAMPLING; SIGNAL INTERFERENCE; SIGNAL RECEIVERS;

ANTIALIASING FILTERS; IN-PHASE QUADRATURE DOWNCONVERTER CIRCUITS; LOCAL OSCILLATOR SAMPLING RATE; PHASE OFFSET; QUADRATURE BALANCE; QUADRATURE SAMPLING METHOD;

FREQUENCY CONVERTER CIRCUITS;

EID: 0033148471     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.769788     Document Type: Article

References (4)

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2. J. Croîs and M.S.J. Steyaert, "A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology," IEEEJ. Solid-State Circuits, vol. 30, pp. 1483-1492, Dec. 1995.
3. A.A. Abidi, "Direct-conversion radio transceivers for digital communications," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 186-187 and 363-364, 1995.
4. G.M. Haller and B.A. Wooley, "A 700-MHz switched-capacitor analog waveform sampling circuit," IEEE J. Solid-State Circuits, vol. 30, pp. 500-508, Apr. 1994.